//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/*************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:  		lcdcontroller.h
**
**  PURPOSE:   		%qEnter module description:$
**
**  LAST MODIFIED: 	sle - 01/11/01
**  EAS VERSION:    2.1
******************************************************************************/

#ifndef _xslcdcontroller_h
#define _xslcdcontroller_h

#ifdef LCD_GLOBALS
#define EXTRN
#else
#define EXTRN extern
#endif

#define LCDCTRL_REG_BASE ((volatile LCDCtrlRegsT *)0x44000000)

// Lcd Controller's Registers definition

struct lccr0Bits {
	unsigned  enb			:1;
	unsigned  cms			:1;
	unsigned  sds			:1;
	unsigned  ldm			:1;
	unsigned  sfm			:1;
	unsigned  ium			:1;
	unsigned  efm			:1;
	unsigned  pas			:1;
	unsigned  ble			:1;
	unsigned  dpd			:1;
	unsigned  dis			:1;
	unsigned  qdm			:1;
	unsigned  pdd			:8;
	unsigned  bm			:1;
	unsigned  oum			:1;
	unsigned  ldt			:1;
	unsigned  rsm			:1;
	unsigned  rtm			:1;
	unsigned  rsvd2			:7;
};

struct lccr1Bits {
	unsigned  ppl			:10;
	unsigned  hsw			:6;
	unsigned  elw			:8;
	unsigned  blw			:8;
};

struct lccr2Bits {
	unsigned  lpp			:10;
	unsigned  vsw			:6;
	unsigned  efw			:8;
	unsigned  bfw			:8;
};

struct lccr3Bits {
	unsigned  pcd			:8;
	unsigned  acb			:8;
	unsigned  api			:4;
	unsigned  vsp			:1;
	unsigned  hsp			:1;
	unsigned  pcp			:1;
	unsigned  oep			:1;
	unsigned  bpp			:3;
	unsigned  dpc			:1;
	unsigned  rsvd0			:4;
};

struct lcsrBits {
	unsigned  lfd			:1;
	unsigned  bau			:1;
	unsigned  ber			:1;
	unsigned  abc			:1;
	unsigned  iol			:1;
	unsigned  iul			:1;
	unsigned  iou			:1;
	unsigned  iuu			:1;
	unsigned  ool			:1;
	unsigned  oul			:1;
	unsigned  oou			:1;
	unsigned  ouu			:1;
	unsigned  rsvd0			:20;
};

typedef struct lcdregs {
  struct lccr0Bits			lccr0;
  struct lccr1Bits			lccr1;
  struct lccr2Bits			lccr2;
  struct lccr3Bits			lccr3;
  VUINT32 reserved1[4] ;   // 0x44000010 thru 0x4400001F
  VUINT32 FBR0 ;  // DMA Channel 0 Frame Branch Register  - 0x4400 0020
  VUINT32 FBR1 ;  // DMA Channel 1 Frame Branch Register  - 0x4400 0024
  VUINT32 reserved2[4] ;   // 0x44000028 thru 0x44000037
  struct lcsrBits			lcsr; 
  VUINT32 LIIDR ; // LCD Controller InterruptID Register  - 0x4400 003C
  VUINT32 TRGBR ; // TMED RGB Seed Register               - 0x4400 0040
  VUINT32 TCR ;   // TMED Control Register                - 0x4400 0044
  VUINT32 reserved3[110] ; // 0x44000048 thru 0x440001FF
  VUINT32 FDADR0 ;// DMA Channel 0 Frame Descriptor Address Register - 0x4400 0200
  VUINT32 FSADR0 ;// DMA Channel 0 Frame Source Address Register     - 0x4400 0204
  VUINT32 FIDR0 ; // DMA Channel 0 Frame ID Register       - 0x4400 0208
  VUINT32 LDCMD0 ;// DMA Channel 0 Command Register        - 0x4400 020C
  VUINT32 FDADR1 ;// DMA Channel 1 Frame Descriptor Address Register - 0x4400 0210
  VUINT32 FSADR1 ;// DMA Channel 1 Frame Source Address Register     - 0x4400 0214
  VUINT32 FIDR1 ; // DMA Channel 1 Frame ID Register       - 0x4400 0218
  VUINT32 LDCMD1 ;// DMA Channel 1 Command Register        - 0x4400 021C
} LcdRegT;

typedef struct LCDFrameDescriptorS {
	UINT32 FDADR;
	UINT32 FSADR;
	UINT32 FIDR;
	UINT32 LDCMD;
} LCDFrameDescriptorT;

typedef enum Panel_PanelType_E {
  Panel_TypeLcd = 1,
  Panel_TypeEncoder = 2
} Panel_PanelType_T;

/* Panel geometry for LCD setup
 */
typedef struct DM_LcdDefinition_S {
  int panelWidth;
  int panelHeight;
  int extraLines;

  char panelType;
  char dualPanel;
  char activeDisplay;
  char colorDepth;

  char horizSyncPW;
  char horizELW;
  char horizBLW;
  //char reserved1;

  char vertSyncPW;
  char vertEFW;
  char vertBFW;
  //char reserved2;

  int  pixelClkDiv;
  char frameSyncPol;
  char horizSyncPol;
  char clockPol;
  char outputEnaPol;

  short acBiasCount;
  //short reserved3;
} DM_LcdDefinition_T;

/* Frame header contains a pointer to the memory region which holds the
 * palette and the pixel data. The palette and pixel data are dependent on
 * the current colorspace and geometry. Keep this structure a multiple of
 * 16 in size.
 */

typedef struct FrameHeaderS {
    int size;                 // Total size of the frame in bytes.
    int horizPixel;
    int vertPixel;
    int extraLines;
    LCDFrameDescriptorT DmaDescriptor;
} FrameHeaderT;

typedef struct FrameS
{
    FrameHeaderT header;
    UINT16 buffer[1];
} FrameT;

extern FrameT *frameP;
extern UINT16 XsLcdBg;       // Background color for character output.
extern UINT16 XsLcdFg;       // Foreground color for character output.
extern UINT8 XsLcdFontScale; // Scaling factor for the font.
extern int XsLcdTask;

/*----------------------------------------------------------------------
 * Statistics
 */
typedef struct LCD_Stats_S {
  int frameCount;

  int iolError;
  int iulError;
  int iouError;
  int iuuError;

  int oolError;
  int oulError;
  int oouError;
  int ouuError;

  int busError;
  int noClear;
} LCD_Stats_T;

/*----------------------------------------------------------------------
 * Pixel clock rates
 */
 
typedef struct LCD_PixelClock_S {
  int clockSpeed;
  int fast;
  int slow;
  int lcd;
} LCD_PixelClock_T;

typedef struct  LcdContextS* LcdContextPT; // Need for dumb single-pass compiler.

/* BEGIN LCD Control Register 0 (LCCR0) definitions */
#define LCD_LCCR0_ENB_LCDEN ( 0x1 << 0 ) /* LCD controller enabled */
#define LCD_LCCR0_CMS_MONO  ( 0x1 << 1 ) /* Monochrome operation */
#define LCD_LCCR0_SDS_DUAL  ( 0x1 << 2 ) /* Dual-panel display enabled */
#define LCD_LCCR0_LDM_NOINT ( 0x1 << 3 ) /* LCD disable done condition does not
                                            generate an interrupt */
#define LCD_LCCR0_SFM_SOFNOINT ( 0x1 << 4 ) /* SOF condition does not
                                               generate an interrupt */
#define LCD_LCCR0_IUM_FIFONOINT ( 0x1 << 5 ) /* Input FIFO underrun errors do
                                                not generate an interrupt*/
#define LCD_LCCR0_EFM_EOFNOINT ( 0x1 << 6 ) /* End of Frame (EOF) does not
                                               generate an interrupt */
#define LCD_LCCR0_PAS_ACTDISP  ( 0x1 << 7 ) /* Active or TFT display op enabled */
#define LCD_LCCR0_BLE_BIGENDN  ( 0x1 << 8 ) /* Big Endian operation enabled */
#define LCD_LCCR0_DPD_DBLPIX   ( 0x1 << 9 ) /* Double pixel operation enabled */
#define LCD_LCCR0_DIS         ( 0x1 << 10 ) /* LCD Controller has been disabled */
#define LCD_LCCR0_QDM_NOINT   ( 0x1 << 11 ) /* QD status does not generate int */
#define LCD_LCCR0_LCDT   ( 0x1 << 22 )
#define LCD_LCCR0_RDSTM   ( 0x1 << 23 )
#define LCD_LCCR0_CMDIM   ( 0x1 << 24 )
// use LCD_LCCR0_PDD_SHIFT and LCD_LCCR0_PDD_MASK to read/write the palette
// DMA request delay fields of LCCR0
#define LCD_LCCR0_PDD_SHIFT   12
#define LCD_LCCR0_PDD_MASK  ( 0xFF << LCD_LCCR0_PDD_SHIFT )

#define LCD_LCCR0_BM_BSNOINT ( 0x1 << 20 ) /* BS condition does not generate int */
#define LCD_LCCR0_OUM_FIFONOINT ( 0x1 << 21 ) /* Output FIFO overrun does not
                                                 generate an interrupt */
/* END LCD Control Register 0 (LCCR0) definitions */

/* BEGIN LCD Control Register 1 (LCCR1) definitions */
// use LCD_LCCR1_PPL_SHIFT and LCD_LCCR1_PPL_MASK to read/write the pixels
// per line fields of LCCR1
#define LCD_LCCR1_PPL_SHIFT   0
#define LCD_LCCR1_PPL_MASK     0x3FF

// use LCD_LCCR1_HSW_SHIFT and LCD_LCCR1_HSW_MASK to read/write the horizontal
// sync pulse width fields of LCCR1
#define LCD_LCCR1_HSW_SHIFT    10
#define LCD_LCCR1_HSW_MASK     ( 0x3F << LCD_LCCR1_HSW_SHIFT )

// use LCD_LCCR1_ELW_SHIFT and LCD_LCCR1_ELW_MASK to read/write the
// end-of-line pixel clock wait count fields of LCCR1
#define LCD_LCCR1_ELW_SHIFT    16
#define LCD_LCCR1_ELW_MASK     ( 0xFF << LCD_LCCR1_ELW_SHIFT )

// use LCD_LCCR1_BLW_SHIFT and LCD_LCCR1_BLW_MASK to read/write the
// beginning-of-line pixel clock wait count fields of LCCR1
#define LCD_LCCR1_BLW_SHIFT    24
#define LCD_LCCR1_BLW_MASK     ( 0xFF << LCD_LCCR1_BLW_SHIFT )

/* END LCD Control Register 1 (LCCR1) definitions */

/* BEGIN LCD Controller Control Register 2 (LCCR2) definitions */
// use LCD_LCCR2_LPP_SHIFT and LCD_LCCR2_LPP_MASK to read/write the
// Lines Per Panel (LPP) fields of LCCR2
#define LCD_LCCR2_LPP_SHIFT    0
#define LCD_LCCR2_LPP_MASK     0x3FF

// use LCD_LCCR2_VSW_SHIFT and LCD_LCCR2_VSW_MASK to read/write the
// Vertical Sync Pulse Width (VSW) fields of LCCR2
#define LCD_LCCR2_VSW_SHIFT    10
#define LCD_LCCR2_VSW_MASK     ( 0x3F << LCD_LCCR2_VSW_SHIFT )

// use LCD_LCCR2_EFW_SHIFT and LCD_LCCR2_EFW_MASK to read/write the
// End-of-Frame line clock wait (EF) count fields of LCCR2
#define LCD_LCCR2_EFW_SHIFT    16
#define LCD_LCCR2_EFW_MASK     ( 0xFF << LCD_LCCR2_EFW_SHIFT )

// use LCD_LCCR2_BFW_SHIFT and LCD_LCCR2_BFW_MASK to read/write the
// Beginning-of-Frame line clock wait (BFW) count fields of LCCR2
#define LCD_LCCR2_BFW_SHIFT    24
#define LCD_LCCR2_BFW_MASK     ( 0xFF << LCD_LCCR2_BFW_SHIFT )

/* END LCD Controller Control Register 2 (LCCR2) definitions */

/* BEGIN LCD Controller Control Register 3 (LCCR3) definitions */
// use LCD_LCCR3_PCD_SHIFT and LCD_LCCR3_PCD_MASK to read/write the
// Pixel Clock Divisor (PCD) fields of LCCR3
#define LCD_LCCR3_PCD_SHIFT    0
#define LCD_LCCR3_PCD_MASK     ( 0xFF << LCD_LCCR3_PCD_SHIFT )

// use LCD_LCCR3_ACB_SHIFT and LCD_LCCR3_ACB_MASK to read/write the
// AC Bias pin frequency fields of LCCR3
#define LCD_LCCR3_ACB_SHIFT    8
#define LCD_LCCR3_ACB_MASK     ( 0xFF << LCD_LCCR3_ACB_SHIFT )

// use LCD_LCCR3_API_SHIFT and LCD_LCCR3_API_MASK to read/write the
// AC Bias Pin trasitions per interrupt field of LCCR3
#define LCD_LCCR3_API_SHIFT    16
#define LCD_LCCR3_API_MASK     ( 0xF << LCD_LCCR3_API_SHIFT )

#define LCD_LCCR3_VSP_ACTLOW  ( 0x1 << 20 ) /* L_FCLK pin is active LOW */
#define LCD_LCCR3_HSP_ACTLOW  ( 0x1 << 21 ) /* L_LCLK pin is active LOW */
#define LCD_LCCR3_PCP_DATSAMPFALL ( 0x1 << 22 ) /* Data sampled on falling edge */
#define LCD_LCCR3_OEP_ACTLOW  ( 0x1 << 23 ) /* L_BIAS pin is active LOW */

// use LCD_LCCR3_BPP_SHIFT and LCD_LCCR3_BPP_MASK to read/write the
// Bits per Pixel (BPP) fields of LCCR3
#define LCD_LCCR3_BPP_SHIFT    24
#define LCD_LCCR3_BPP_MASK     ( 0x7 << LCD_LCCR3_BPP_SHIFT )

#define LCD_LCCR3_BPP_1      ( 0x1 << LCD_LCCR3_BPP_SHIFT ) /*  1 bit per pixel */
#define LCD_LCCR3_BPP_2      ( 0x2 << LCD_LCCR3_BPP_SHIFT ) /*  2 bits per pixel */
#define LCD_LCCR3_BPP_4      ( 0x4 << LCD_LCCR3_BPP_SHIFT ) /*  4 bits per pixel */
#define LCD_LCCR3_BPP_8      ( 0x8 << LCD_LCCR3_BPP_SHIFT ) /*  8 bits per pixel */
#define LCD_LCCR3_BPP_16     ( 0xF << LCD_LCCR3_BPP_SHIFT ) /* 16 bits per pixel */

#define LCD_LCCR3_DPC_DBLFRQ  ( 0x1 << 27 ) /* Double pixel clock mode */
/* END LCD Controller Control Register 3 (LCCR3) definitions */

/* BEGIN LCD DMA Channel Frame Descriptor Address Registers (FDADRx) definitions */
#define LCD_FDADR_MASK 0xFFFFFFF0
/* END LCD DMA Channel Frame Descriptor Address Registers (FDADRx) definitions */

/* BEGIN LCD DMA Channel Frame Source Address Registers (FSADRx) definitions */
#define LCD_FSADR_MASK 0xFFFFFFF8
/* END LCD DMA Channel Frame Descriptor Address Registers (FSADRx) definitions */

/* BEGIN LCD DMA Frame ID Registers (FIDRx) definitions */
#define LCD_FIDR_MASK 0xFFFFFFF8
/* END LCD DMA Frame ID Registers (FIDRx) definitions */

/* BEGIN LCD DMA Command Registers (LDCMDx) definitions */
#define LCD_LDCMD_PAL_LENGTH   0xFFFFF    /* mask for accessing only the length */
#define LCD_LDCMD_EOFInt    ( 0x1 << 21 ) /* Set the end of frame (EOF) interrupt
                                             bit in the LCD status reg when finished 
                                             fetching last word of this frame */
#define LCD_LDCMD_SOFInt    ( 0x1 << 21 ) /* Set the start of frame (SOF) interrupt
                                             bit in the LCD status reg when starting 
                                             a new frame */

// bits 27-31 reserved

#define LCD_LDCMD_PAL_ACTFETCH  ( 0x1 << 26 ) /* Tells DMA controller this is the
                                                 palette buffer being fetched */
/* END LCD DMA Command Registers (LDCMDx) definitions */

/* BEGIN LCD DMA Frame Branch Registers (FBRx) definitions */
#define LCD_FBR_BRA_AFTER   ( 0x1 << 0 )  /* Branch after finishing frame */
#define LCD_FBR_BINT_SETBS  ( 0x1 << 1 )  /* Set branc status (BS) int bit in LCD
                                             controller after branched-to-descr
                                             is loaded */
// bits 2-3 reserved

#define LCD_FBR_SRCADDR_SHIFT   4
#define LCD_FBR_SRCADDR_MASK    0xFFFFFFF8 
/* END LCD DMA Frame Branch Registers (FBRx) definitions */

/* BEGIN LCD Controller Status Register (LCSR) definitions */
#define LCD_LCSR_LDD_DISDON ( 0x1 << 0 ) /* LCD disabled and last frame complete */ 
#define LCD_LCSR_SOF_STRT   ( 0x1 << 1 ) /* DMA fetching new frame & SOFint set */
#define LCD_LCSR_BER_ERR    ( 0x1 << 2 ) /* DMA attempted unallowed memory access*/
#define LCD_LCSR_ABC_CNTR0  ( 0x1 << 3 ) /* AC transition cntr decr'ed to zero */
#define LCD_LCSR_IUL_UNRUN  ( 0x1 << 4 ) /* In FIFO underrun lwr panel status */
#define LCD_LCSR_IUU_UNRUN  ( 0x1 << 5 ) /* In FIFO underrun upper panel status */
#define LCD_LCSR_OU_UNRUN   ( 0x1 << 6 ) /* Out FIFO underrun status */
#define LCD_LCSR_QD_LCDDIS  ( 0x1 << 7 ) /* LCD has been quickly disabled */
#define LCD_LCSR_EOF_DMADON ( 0x1 << 8 ) /* DMA finished frame with EOFInt set */
#define LCD_LCSR_BS_BINTSET ( 0x1 << 9 ) /* The DMA has loaded a branch descriptor
                                            and set the BINT bit in the frame
                                            branch register */
#define LCD_LCSR_SINT_ERR   ( 0x1 << 19 ) /* Error interrupt has occurred before
                                             previous interrupt cleared */
// bits 11-31 reserved
/* END LCD Controller Status Register (LCSR) definitions */


/* BEGIN LCD Controller Interrupt ID Register (LIIDR) definitions */
#define LCD_LIIDR_FRAMEID_MASK  0xFFFFFFF8
/* END LCD Controller Interrupt ID Register (LIIDR) definitions */

/* BEGIN LCD TMED RGB Seed Register (TRGBR) definitions */
// Use the following for accesses to the RGB fields in the TRGBR register
#define LCD_TRGR_TRS_MASK   0xFF

#define LCD_TRGR_TGS_SHIFT  8
#define LCD_TRGR_TGS_MASK   ( 0xFF << LCD_TRGR_TGS_SHIFTS )

#define LCD_TRGR_TBS_SHIFT  16
#define LCD_TRGR_TBS_MASK   ( 0xFF << LCD_TRGR_TBS_SHIFT )

// bits 24-31 reserved
/* END LCD TMED RGB Seed Register (TRGBR) definitions */

/* BEGIN LCD TMED Control Register (TCR) definitions */
#define LCD_TCR_TM2S_SCH2  ( 0x1 << 0 ) /* selects TMED Method 2 scheme 2 */
#define LCD_TCR_TM1S_SCH2  ( 0x1 << 1 ) /* selects TMED Method 1 scheme 2 */
#define LCD_TCR_TM2En      ( 0x1 << 2 ) /* TMED Method 2 enable */
#define LCD_TCR_TM1En      ( 0x1 << 3 ) /* TMED Method 1 enable */

#define LCD_TCR_TVBS_SHIFT   4
#define LCD_TCR_TVBS_MASK ( 0xF << LCD_TCR_TVBS_SHIFT ) /* Block shift val mask
                                                             for vertical beat
                                                             suppression */
#define LCD_TCR_THBS_SHIFT   8
#define LCD_TCR_THBS_MASK ( 0xF << LCD_TCR_THBS_SHIFT ) /* Block shift val mask
                                                             for horizontal beat
                                                             suppression */

// begin defines for TMED Shades per Color (TSCS) fields of TCR register
#define LCD_TCR_TSCS_SHIFT   12
#define LCD_TCR_TSCS_MASK  ( 0x3 << LCD_TCR_TSCS_SHIFT ) /* mask for TSCS fields */

#define LCD_TCR_TSCS_33     ( 0x0 << LCD_TCR_TSCS_SHIFT ) /* 33 red,65 green,33 blue */
#define LCD_TCR_TSCS_65     ( 0x1 << LCD_TCR_TSCS_SHIFT ) /* 65 red,65 green,65 blue */
#define LCD_TCR_TSCS_129    ( 0x2 << LCD_TCR_TSCS_SHIFT ) /* 129 red,129 green,129 blue */
#define LCD_TCR_TSCS_256    ( 0x3 << LCD_TCR_TSCS_SHIFT ) /* 256 red,256 green,256 blue */
// begin defines for TMED Shades per Color (TSCS) fields of TCR register

#define LCD_TCR_TED_ENDIST2 ( 0x1 << 14 ) /* selects energy dist scheme 2 */ 

// bits 15-31 reserved
/* END LCD TMED Control Register (TCR) definitions */

#define LCD_TCR_RECOMMENDED   0x0000754F /* As stated in the EAS for Cotulla */

typedef struct LCDCtrlRegsS
{
    VUINT32 LCCR0 ; // LCD Controller Control register 0    - 0x4400 0000
    VUINT32 LCCR1 ; // LCD Controller Control register 1    - 0x4400 0004
    VUINT32 LCCR2 ; // LCD Controller Control register 2    - 0x4400 0008
    VUINT32 LCCR3 ; // LCD Controller Control register 3    - 0x4400 000C
    VUINT32 reserved1[4] ;   // 0x44000010 thru 0x4400001F
    VUINT32 FBR0 ;  // DMA Channel 0 Frame Branch Register  - 0x4400 0020
    VUINT32 FBR1 ;  // DMA Channel 1 Frame Branch Register  - 0x4400 0024
    VUINT32 reserved2[4] ;   // 0x44000028 thru 0x44000037
    VUINT32 LCSR ;  // LCD Controller Status Register       - 0x4400 0038
    VUINT32 LIIDR ; // LCD Controller InterruptID Register  - 0x4400 003C
    VUINT32 TRGBR ; // TMED RGB Seed Register               - 0x4400 0040
    VUINT32 TCR ;   // TMED Control Register                - 0x4400 0044
    VUINT32 reserved3[110] ; // 0x44000048 thru 0x440001FF
    VUINT32 FDADR0 ;// DMA Channel 0 Frame Descriptor Address Register - 0x4400 0200
    VUINT32 FSADR0 ;// DMA Channel 0 Frame Source Address Register     - 0x4400 0204
    VUINT32 FIDR0 ; // DMA Channel 0 Frame ID Register       - 0x4400 0208
    VUINT32 LDCMD0 ;// DMA Channel 0 Command Register        - 0x4400 020C
    VUINT32 FDADR1 ;// DMA Channel 1 Frame Descriptor Address Register - 0x4400 0210
    VUINT32 FSADR1 ;// DMA Channel 1 Frame Source Address Register     - 0x4400 0214
    VUINT32 FIDR1 ; // DMA Channel 1 Frame ID Register       - 0x4400 0218
    VUINT32 LDCMD1 ;// DMA Channel 1 Command Register        - 0x4400 021C
} LCDCtrlRegsT;

typedef struct BmpS {
    INT8 header[0x36];
    struct pixelS {
        UINT8 blue;
        UINT8 green;
        UINT8 red;
    } pixel[1];
} BmpT;


void XsLcdBackLightOn(void);
void XsLcdSWInit(void);
ErrorT XsLcdHWSetup(void);
void XsLcdOn(void);
void XsLcdClear(void);
UINT16 XsLcdRGB565(UINT8 red, UINT8 green, UINT8 blue);
void XsLcdChar(CHAR c);
void XsLcdStr(PCHAR s);
void XsLcdOut(void);
void XsLcdPutXY(UINT16 x, UINT16 y, UINT16 p);
void XsLcdScroll(void);
BOOL XsLcdBmp(BmpT *bmpP);

#undef EXTRN
#endif /* _lcdcontroller_h */